SAVE is a European collaborative research project funded within the Seventh Framework Programme(FP7) aimed at the development of software/hardware technologies for an efficient exploitation of heterogeneous system architectures. In the SAVE project HW/SW/OS components are developed that allow for deciding at runtime the mapping of the computation kernels on the appropriate type of resource, based on the current system context and requirements. Dr. George Kornaros’s research group has participated in the European FP7 research project SAVE, which has been completed successfully. Please find below the official press release.
Today marks the completion of the SAVE project, which challenged a team of engineers and researchers to explore how complex hardware systems can more efficiently execute data intensive applications. Funded by the European Union, SAVE has led to a number of innovations in hardware, software and operating system (OS) components. When integrated together, they can reduce application deployment costs and maximize usage of heterogeneous system computing units, resulting in energy efficiency being improved by up to twenty per cent.
A range of complex electronic systems stands to benefit from these innovations, including computer data centers, consumer electronics, automotive products and complex industrial electronics.
The computing units can be on chip, for example central processing units (CPUs) ranging from small and low-power to high-end and efficient, graphics processing units (GPUs), and dedicated accelerators. Alternatively, the units can be off chip, such as racks of dedicated accelerators or field-programmable gate arrays (FPGAs).The prototyped technologies will enable performance and energy-efficiency gains in high-performance computing (HPC) and embedded heterogeneous systems.
Key achievements include:
Platform behavior monitoring and task dispatching hardware and software: the first toolset closely tracks the performance and use rate of the various computing units available in the heterogeneous systems. The second toolset decides which computing units are best suited for the job.
Just-in-Time compilation technology: using SAVE technologies, at runtime, a single application-code representation is optimized to the many possible hardware targets of the platform: CPUs, GPUs, accelerators, FPGAs.
Hardware and software virtualization technologies: these technologies efficiently expose the dedicated processing engines to the many virtual machines (VM) running on these systems.
The teams successfully prototyped virtualized GPUs, virtualized FPGA-based data-flow engines (DFEs), and virtualized application-specific accelerators.
These innovations are the culmination of three years of collaborative research by a team of three academic and four industrial partners. The international team worked together to achieve dynamic optimization of workload assignments across multicore system computation units, operated simultaneously from several virtualized operating systems. These developments lay the foundations for industrial partners to further optimize ever more complex systems, including HPC systems for finance applications and automotive embedded systems.Funded by the European Commission’s Seventh Framework Program (FP7), the project was launched on 01 September 2013, under the project name SAVE: ‘Self-Adaptive Virtualization-Aware High-Performance/Low-Energy Heterogeneous System Architectures.’
SAVE innovations enable the dynamic optimization of task assignments across processing units operated from several OSes, all from single code representation of each application.
Partners’ views on the SAVE project
Politecnico di Milano (Italy, SAVE project coordinator)
“Dynamic trade-offs in performance and energy are becoming increasingly synonymous with heterogeneous system management. Within the SAVE project, researchers designed self-adaptive software components and associated optimization policies to manage at runtime the resources offered by the heterogeneous computing systems developed by our hardware vendor partners.”
Prof. Cristiana Bolchini, Professor, Dipartimento di Elettronica Informazione e Bioingegneria, Politecnico di Milano,
ARM (United Kingdom)
“The next generation of graphics technology and smart connected products will require the optimized execution of simultaneous compute-intensive tasks through several operating systems. The ARM team’s focus on the SAVE project was to prototype virtualization technologies and identify pathways to maximize system efficiency in emerging GPU use cases in markets such as automotive and HPC.”
Eric Hennenhoefer, Vice President, Research, ARM
Maxeler Technologies (United Kingdom)
“Self-adaptive behavior and dynamic resource allocation is key to improving performance and efficiency in heterogeneous HPC systems with dedicated DFEs. Adding orchestration and virtualization to Maxeler’s dataflow computers helps us to efficiently run large dynamic workloads in a multitenant environment, a technology that is highly promising for a range of users in finance, science and engineering.”
Georgi Gaydadjiev, Vice President, Dataflow Software Engineering
“In complex heterogeneous multicore systems, managing data communication efficiently and securely between host processors, on-chip computing units (such as the GPU and hardware accelerators) and off-chip islands of computation is key to providing power-efficient and fast dynamic kernel offloading. SAVE has brought the task of optimizing heterogeneous System-on-Chip solutions much closer to full industrialization.”
Philippe Quinio, Group Vice President, IP Sourcing and Strategy, STMicroelectronics
Technological Educational Institute of Crete (Greece)
“Two key components for self-adaptive heterogeneous system architecture are the hardware resource usage monitoring mechanisms and the workload dispatch mechanisms. By working closely with hardware vendors, we designed low-level communication solutions between the general purpose CPUs and the specialized computation units like GPUs and DFEs.”
Dr George Kornaros, Professor, Technological Educational Institute of Crete
Paderborn University (Germany)
“A key obstacle for best use of heterogeneous computing is the manual effort to optimize code for each hardware resource type. Our autonomous runtime and compilation system removes this burden: critical parts of applications are automatically identified and they are seamlessly translated and optimized for execution on GPU and FPGAs accelerators. With SAVE, Paderborn University paved the way for wider deployment of the underlying technologies, namely, static and dynamic code analysis and just-in-time code generation techniques.”
Dr Christian Plessl, Professor, Paderborn University
Virtual Open Systems
“The SAVE project has been for Virtual Open Systems the testing ground to demonstrate that hardware assisted virtualization and innovative hypervisor extensions are able to provide near native performance, thus paving the way for extensive usage of virtualization of programmable accelerators in many market segments. The SAVE project has strengthened the company’s position in the open-source community, while creating new business opportunities in both product and service lines.”
Energy-Performance Considerations for Data Offloading to FPGA-based Accelerators over PCIe
D. Bakoyannis, O. Tomoutzoglou and G. Kornaros,
ACM Transactions on Architecture and Code Optimization (TACO), Vol 15, 1, Apr 2018, Article 14
Efficient Dispatching to Co-processors over PCIe
D. Bakoyannis, O. Tomoutzoglou, G. Kornaros and M. Coppola
in Proc. HiPEAC Workshop on Reconfigurable Computing, WRC, pp. 1-4, 2016 [Preprint]
Adaptive Memory Management Scheme for MMU-Less Embedded Systems
Ioannis Deligiannis and George Kornaros,
In 11th IEEE International Symposium on Industrial Embedded Systems, 23 – 25 May 2016, Krakow, Poland
VWQS: a Dispatching Mechanism of Variable-Size Tasks in Heterogeneous Systems
George Kornaros and Menelaos Pratikakis ,
The International Conference on High Performance Computing & Simulation, (HPCS 2016) 14th Annual Meeting, July 18 – 22, 2016, Innsbruck, Austria
Efficient Communication in Heterogeneous SoCs with Unified Address Space
Othon Tomoutzoglou, Dimitrios Mbakoyannis, Georgios Kornaros and Marcello Coppola
11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), June 27-29, 2016, Tallinn – ESTONIA [IEEEXplore]
Invited presentation: NoC services modelled in GEM5 for High Performance MPSoC
In Nanoelectronics, Applications, Design & Technology Conference 2016 (http://tima.imag.fr/sls/dtc/)
Runtime Adaptation of Embedded Tasks with A-Priori Known Timing Behavior Utilizing On-Line Partner-Core Monitoring and Recovery
I. Christoforakis, O. Tomoutzoglou, D. Bakoyiannis, G. Kornaros,
Proc. Int. Conf. on Embedded and Ubiquitous Computing, EUC, pp. 1-8, 2014